------------------------------------------------------------------------------- -- (C) Bibix -- The content below includes confidential, proprietary information of -- Bibix. All use, disclosure, and/or reproduction is prohibited -- unless authorized in writing. All rights reserved. ------------------------------------------------------------------------------- -- File : tb_cordic_pipe.vhd -- Description : VHDL testbench for cordic_pipe model -- Author : Sabih Gerez, Bibix -- based on work by Rene Moll, DSE -- Creation date: August 14, 2011 ------------------------------------------------------------------------------- -- $Rev: 146 $ -- $Author: sabih $ -- $Date: 2011-08-18 23:57:22 +0200 (Thu, 18 Aug 2011) $ -- $Log$ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- sg_cordic_rotation: the stimuli generator for cordic_pipe ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity sg_cordic_pipe is port( clock : out std_logic; resetn : out std_logic; x_in : out std_logic_vector(9 downto 0); y_in : out std_logic_vector(9 downto 0); p_in : out std_logic_vector(9 downto 0); op_mode : out std_logic; x_out : in std_logic_vector(10 downto 0); y_out : in std_logic_vector(10 downto 0); p_out : in std_logic_vector(9 downto 0) ); end sg_cordic_pipe; architecture behavior of sg_cordic_pipe is -- internal clock signal (this signal is necessary -- because VHDL does not allow that output signals are read in the -- entity that generates them) signal clk_i: std_logic; -- input file file in_file: text open read_mode is "cordic_pipe.in"; -- output file file out_file: text open write_mode is "cordic_pipe.out"; begin -- connect internal clock and reset to ports clock <= clk_i; -- generate clock clock_gen: process constant half_clock_period: time := 100 ns; begin clk_i <= '1'; wait for half_clock_period; clk_i <= '0'; wait for half_clock_period; end process clock_gen; -- The hardware registers are clocked on the rising edge of the -- clock; the stimuli should be stable then and therefore change -- on the falling edge of the clock. -- Note that the first edge of the clock is a falling one. stimuli: process (clk_i) variable first: boolean := true; variable inline, outline: line; variable good: boolean; variable in_X, in_Y, in_P: integer; variable in_om: std_logic; constant CHAR_SPACE: character := ' '; begin if falling_edge(clk_i) then -- handle reset; reset signal is high during first clock cycle only if first then first := false; resetn <= '0'; else resetn <= '1'; -- handle input signal, take it from file assert not endfile(in_file) report "OK! Simulation stopped at end of input file." severity failure; readline(in_file, inline); read(inline, in_X); read(inline, in_Y); read(inline, in_P); read(inline, in_om); x_in <= std_logic_vector(to_signed(in_X, 10)); y_in <= std_logic_vector(to_signed(in_Y, 10)); p_in <= std_logic_vector(to_signed(in_P, 10)); op_mode <= in_om; -- handle output write(outline, to_integer(signed(x_out))); write(outline, CHAR_SPACE); write(outline, to_integer(signed(y_out))); write(outline, CHAR_SPACE); write(outline, to_integer(signed(p_out))); writeline(out_file, outline); end if; -- first end if; -- falling_edge(clk_i) end process stimuli; end architecture; ------------------------------------------------------------------------------- -- tb_cordic_rotation: the testbench, instantiating DUV and stimuli -- generator (SG) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tb_cordic_pipe is end entity; architecture structure of tb_cordic_pipe is -- DUV component cordic_pipe_std port( clock : in std_logic; resetn : in std_logic; x_in : in std_logic_vector(9 downto 0); y_in : in std_logic_vector(9 downto 0); p_in : in std_logic_vector(9 downto 0); op_mode : in std_logic; x_out : out std_logic_vector(10 downto 0); y_out : out std_logic_vector(10 downto 0); p_out : out std_logic_vector(9 downto 0) ); end component; -- SG component sg_cordic_pipe port( clock : out std_logic; resetn : out std_logic; x_in : out std_logic_vector(9 downto 0); y_in : out std_logic_vector(9 downto 0); p_in : out std_logic_vector(9 downto 0); op_mode : out std_logic; x_out : in std_logic_vector(10 downto 0); y_out : in std_logic_vector(10 downto 0); p_out : in std_logic_vector(9 downto 0) ); end component; -- interconnection signals signal clock : std_logic; signal resetn : std_logic; signal x_in : std_logic_vector(9 downto 0); signal y_in : std_logic_vector(9 downto 0); signal p_in : std_logic_vector(9 downto 0); signal op_mode : std_logic; signal x_out : std_logic_vector(10 downto 0); signal y_out : std_logic_vector(10 downto 0); signal p_out : std_logic_vector(9 downto 0); begin duv: cordic_pipe_std port map (clock => clock , resetn => resetn , x_in => x_in , y_in => y_in , p_in => p_in , op_mode => op_mode , x_out => x_out , y_out => y_out , p_out => p_out ); sg: sg_cordic_pipe port map (clock => clock , resetn => resetn , x_in => x_in , y_in => y_in , p_in => p_in , op_mode => op_mode , x_out => x_out , y_out => y_out , p_out => p_out ); end structure;