------------------------------------------------------------------------------- -- (C) Bibix -- The content below includes confidential, proprietary information of -- Bibix. All use, disclosure, and/or reproduction is prohibited -- unless authorized in writing. All rights reserved. ------------------------------------------------------------------------------- -- File : tb_cordic_sine_gen.vhd -- Description : VHDL testbench for cordic_sine_gen model -- Author : Sabih Gerez, Bibix -- based on work by Rene Moll, DSE -- Creation date: August 14, 2011 ------------------------------------------------------------------------------- -- $Rev: 146 $ -- $Author: sabih $ -- $Date: 2011-08-18 23:57:22 +0200 (Thu, 18 Aug 2011) $ -- $Log$ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- sg_cordic_rotation: the stimuli generator for cordic_sine_gen ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity sg_cordic_sine_gen is port( clock : out std_logic; resetn : out std_logic; phase_step : out std_logic_vector(9 downto 0); x_out : in std_logic_vector(10 downto 0); y_out : in std_logic_vector(10 downto 0) ); end sg_cordic_sine_gen; architecture behavior of sg_cordic_sine_gen is -- internal clock signal (this signal is necessary -- because VHDL does not allow that output signals are read in the -- entity that generates them) signal clk_i: std_logic; -- input file file in_file: text open read_mode is "cordic_sine_gen.in"; -- output file file out_file: text open write_mode is "cordic_sine_gen.out"; begin -- connect internal clock and reset to ports clock <= clk_i; -- generate clock clock_gen: process constant half_clock_period: time := 100 ns; begin clk_i <= '1'; wait for half_clock_period; clk_i <= '0'; wait for half_clock_period; end process clock_gen; -- The hardware registers are clocked on the rising edge of the -- clock; the stimuli should be stable then and therefore change -- on the falling edge of the clock. -- Note that the first edge of the clock is a falling one. stimuli: process (clk_i) variable first: boolean := true; variable inline, outline, screenline: line; variable good: boolean; variable in_P: integer; variable screen_str: string (1 to 80); constant CHAR_SPACE: character := ' '; variable xpos, ypos: integer; begin if falling_edge(clk_i) then -- handle reset; reset signal is high during first clock cycle only if first then first := false; for i in 1 to 80 loop screen_str(i) := ' '; end loop; resetn <= '0'; else resetn <= '1'; -- handle input signal, take it from file assert not endfile(in_file) report "OK! Simulation stopped at end of input file." severity failure; readline(in_file, inline); read(inline, in_P); phase_step <= std_logic_vector(to_signed(in_P, 10)); -- handle output write(outline, to_integer(signed(x_out))); write(outline, CHAR_SPACE); write(outline, to_integer(signed(y_out))); writeline(out_file, outline); -- ascii art screen output xpos := integer(real(40) + 40.0/(512*1.7)*real(to_integer(signed(x_out)))); ypos := integer(real(40) + 40.0/(512*1.7)*real(to_integer(signed(y_out)))); screen_str(xpos) := '*'; screen_str(ypos) := '+'; write(screenline, screen_str); writeline(output, screenline); screen_str(xpos) := ' '; screen_str(ypos) := ' '; end if; -- first end if; -- falling_edge(clk_i) end process stimuli; end architecture; ------------------------------------------------------------------------------- -- tb_cordic_rotation: the testbench, instantiating DUV and stimuli -- generator (SG) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity tb_cordic_sine_gen is end entity; architecture structure of tb_cordic_sine_gen is -- DUV component cordic_sine_gen_std port( clock : in std_logic; resetn : in std_logic; phase_step : in std_logic_vector(9 downto 0); x_out : out std_logic_vector(10 downto 0); y_out : out std_logic_vector(10 downto 0) ); end component; -- SG component sg_cordic_sine_gen port( clock : out std_logic; resetn : out std_logic; phase_step : out std_logic_vector(9 downto 0); x_out : in std_logic_vector(10 downto 0); y_out : in std_logic_vector(10 downto 0) ); end component; -- interconnection signals signal clock : std_logic; signal resetn : std_logic; signal phase_step : std_logic_vector(9 downto 0); signal x_out : std_logic_vector(10 downto 0); signal y_out : std_logic_vector(10 downto 0); begin duv: cordic_sine_gen_std port map (clock => clock , resetn => resetn , phase_step => phase_step , x_out => x_out , y_out => y_out); sg: sg_cordic_sine_gen port map (clock => clock , resetn => resetn , phase_step => phase_step , x_out => x_out , y_out => y_out); end structure;