------------------------------------------------------------------------------- -- (C) Bibix -- The content below includes confidential, proprietary information of -- Bibix. All use, disclosure, and/or reproduction is prohibited -- unless authorized in writing. All rights reserved. ------------------------------------------------------------------------------- -- File : tb_fft_r8_bf.vhd -- Description : VHDL testbench for radix 2^3 butterfly -- Author : Sabih Gerez, Bibix -- based on work by Rene Moll, DSE -- Creation date: October 31, 2011 ------------------------------------------------------------------------------ -- $Rev: 174 $ -- $Author: sabih $ -- $Date: 2011-11-03 23:03:29 +0100 (Thu, 03 Nov 2011) $ -- $Log$ ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Testbench for a radix-2^3 butterfly -- -- Requires files from the C++ testbench for input: -- + fft_r8_bf.in -- -- Output is written to: -- + fft_r8_bf.out -- + and should be exactly equal to fft_r8_bf.ref ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- package sg_pack: data sizes for stimuli generator ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package sg_pack is constant word_length: integer := 12; end package; ------------------------------------------------------------------------------- -- stimuli generator: -- + reads test vectors from file -- + performs type conversions -- + writes results to file ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_textio.all; library std; use std.textio.all; use work.sg_pack.all; entity sg_fft_r8_bf is port( clock : out std_logic; resetn : out std_logic; data_in_real : out std_logic_vector(word_length-1 downto 0); data_in_imag : out std_logic_vector(word_length-1 downto 0); data_out_real : in std_logic_vector(word_length-1 downto 0); data_out_imag : in std_logic_vector(word_length-1 downto 0) ); end entity; architecture behavior of sg_fft_r8_bf is -- Used for output formatting constant CHAR_SPACE: character := ' '; -- Internally generated clock signal clk_i : std_logic; -- Open input and twiddle files for DUV input file in_file: text open read_mode is "fft_r8_bf.in"; -- Open output file for DUV results file out_file: text open write_mode is "fft_r8_bf.out"; begin clock <= clk_i; -- generate clock clock_gen: process constant half_clock_period: time := 100 ns; begin clk_i <= '1'; wait for half_clock_period; clk_i <= '0'; wait for half_clock_period; end process clock_gen; -- read input data from file and store results in output file stimuli : process(clk_i) variable first : boolean := true; variable inline, outline : line; variable in_data_real, in_data_imag : integer; begin if (falling_edge(clk_i)) then if (first = true) then first := false; resetn <= '0'; else resetn <= '1'; -- Read one complex sample assert not endfile(in_file) report "OK! Simulation stopped at end of input file!" severity failure; readline(in_file, inline); read(inline, in_data_real); data_in_real <= std_logic_vector(to_signed(in_data_real, WORD_LENGTH)); read(inline, in_data_imag); data_in_imag <= std_logic_vector(to_signed(in_data_imag, WORD_LENGTH)); -- Write output to file write(outline, to_integer(signed(data_out_real))); write(outline, CHAR_SPACE); write(outline, to_integer(signed(data_out_imag))); writeline(out_file, outline); end if; end if; end process stimuli; end architecture; library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- -- Testbench: connect design-under verification with stimuli generator ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.sg_pack.all; entity tb_fft_r8_bf is end entity; architecture structural of tb_fft_r8_bf is -- Routing signals signal clock, resetn : std_logic; signal data_in_real, data_in_imag : std_logic_vector(word_length-1 downto 0); signal data_out_real, data_out_imag: std_logic_vector(word_length-1 downto 0); -- DUV component fft_r8_bf_std is port( clock : in std_logic; resetn : in std_logic; x_real : in std_logic_vector(word_length-1 downto 0); x_imag : in std_logic_vector(word_length-1 downto 0); y_real : out std_logic_vector(word_length-1 downto 0); y_imag : out std_logic_vector(word_length-1 downto 0) ); end component; -- SG component sg_fft_r8_bf is port( clock : out std_logic; resetn : out std_logic; data_in_real : out std_logic_vector(word_length-1 downto 0); data_in_imag : out std_logic_vector(word_length-1 downto 0); data_out_real : in std_logic_vector(word_length-1 downto 0); data_out_imag : in std_logic_vector(word_length-1 downto 0) ); end component; begin duv : fft_r8_bf_std port map ( clock => clock, resetn => resetn, x_real => data_in_real, x_imag => data_in_imag, y_real => data_out_real, y_imag => data_out_imag ); tvg : sg_fft_r8_bf port map ( clock => clock, resetn => resetn, data_in_real => data_in_real, data_in_imag => data_in_imag, data_out_real => data_out_real, data_out_imag => data_out_imag ); end architecture;