component top wl: generic integer = 12 T_in : generic type = signed(wl , 1) T_out: generic type = signed(wl-2, 1, sat, round) T_sum: generic type = signed(wl+5, 6) clear: in bit data_in : in T_in data_out: out T_out variable sum: T_sum register r: T_sum = 0 begin if clear == 1 sum = data_in else sum = r + data_in end r = sum data_out = r end