# subcomponent component reg word_length: generic integer = 8 T_IO : generic type = signed(word_length) data_in : in T_IO data_out : out T_IO register storage : T_IO = 0 begin storage = data_in data_out = storage end # top-level component component top word_length: generic integer = 12 T_topIO : generic type = bitvector(word_length) data_in : in T_topIO data_out : out T_topIO type T_num: signed(word_length) variable data_internal: T_topIO r2_in, r2_out: T_num generate r1: reg T_IO = T_topIO data_in => data_in data_out => data_internal r2: reg word_length = word_length data_in => r2_in data_out => r2_out begin r2_in = reinterpret(T_num, data_internal) data_out = reinterpret(T_topIO, r2_out) end