Register-Transfer-Level DSP Design with Arx
Digital signal processing algorithms can be implemented on many platforms such as general-purpose processors, digital signal processors, GPUs, very-large instruction word processors, but also on dedicated hardware. This course is about the latter category and addresses the development of signal-processing hardware at the register-transfer level (RTL, RT level) for an ASIC or FPGA.
Often the verification and optimization of the implementation of a DSP algorithm requires extensive simulations. For the purpose of simulation efficiency, these simulations are not carried out on the basis of descriptions in HDLs such as VHDL or Verilog, but by means of system-level models in C or Matlab. This means that effort needs to be spent to maintain system-level descriptions and HDL code of the same hardware. Arx, a domain-specific language developed at the University of Twente, circumvents this problem by having a single description from which both system-level descriptions as HDL can be generated.
This course is a practical introduction to DSP implementations at the register-transfer level. Arx is used as a vehicle to illustrate the concepts that are presented.
The target audience for this course is the engineer who wants to learn DSP design at the RT level. This could be a DSP specialist without experience in RTL implementations, a digital or analog IC designer without experience in DSP, etc. The participant is assumed to have basic knowledge about RT-level design, e.g. as taught in the course Fundamentals of RTL Digital Design. Some basic understanding of programming in C or C++ will also be helpful.
Wrap-up of RTL design. Basics of DSP implementation. Synchronous data flow. Transformations: pipelining, retiming, folding and unfolding. One-to-one mapping versus resource sharing.
Number representation, unsigned and signed integers, fixed-point numbers. Fixed-point optimization.
The Arx language. Components, data types, expressions, functions, etc.
Arx implementations of DSP building blocks. FIR and IIR filters, CORDIC, FFT pipeline.
System-level testbench design with IT++.
Design and simulation of a GFSK receiver in Arx and IT++.
Course Organization and Material
This course could be organized as a 2-day event with some 4 hours of lectures and some 10 to 12 hours of practical exercises. Alternatively, one could think of three evening sessions of three hours each and exercises to be done as homework.
The course material will consist of the presented slides and possibly some additional documents.