## Fundamentals of Register-Transfer-Level Digital Design

### Information

This is an elementary course in digital hardware design. It offers an introduction to binary functions, combinational and sequential logic design, finite-state machines, number representation, basic circuits for for arithmetic, the distinction between datapaths and controllers, etc.

Current-day digital design relies entirely on
*logic-synthesis* techniques. This means that the behavior of
the hardware is specified in a *hardware description language*
(HDL) such as VHDL or Verilog. This behavior is the input for a
logic-synthesis tool which converts it in building blocks of the
target technology such as NAND gates and flipflops.

A common abstraction level for logic synthesis is
the so-called *register-transfer level* (RTL or RT level). The
RTL view of hardware amounts to distinguishing storage elements
(registers) the state of which change at the rising edge of a clock,
and combinational logic that compute the next state.

This course addresses exactly digital hardware design at the RT level and provides the foundations for more advanced courses.

### Audience

The target audience for this course is a professional with a formation outside electrical engineering, e.g. a physicist, mathematician or mechanical engineer. The course is at undergraduate level. An interested student with a solid secondary school degree and basic computer-operation skills should be able to understand the theory and perform the exercises.

### Contents

Binary signals, Boolean functions, combinational logic, sum-of-products and product-of-sums form, multilevel Boolean functions.

Number representations, adders and multipliers.

Sequential logic, clock signal, positive edge-triggered flipflop.

Technology building blocks for ASICs (standard cells) and FPGAs (LUTs, etc.).

Datapaths and controllers, finite-state machines, concept of parallel processing.

Hardware description languages: VHDL and/or Verilog.

Logic synthesis, timing constraints, critical path. Tool: e.g. Altera Quartus Web Edition.

Testbench concept, pre-synthesis and post-synthesis simulation.

### Course Organization and Material

This course requires about 40 hours of effort by the student. This time is partitioned in about 10 hours of theory and 30 hours of practical exercises. It could e.g. be organized as a full-week course with 10 blocks of 1 + 3 hours for a lecture and exercises in the mornings and afternoons. Alternatively, it could e.g. be organized as 5 weekly evening sessions of 2 hour lectures, 1 hour on-site practice and 5 hours of homework.

The study material will consist of lecture slides and possibly a book.