Single-File IP

This page contains designs coded in Arx that are less trivial than the examples embedded in the Arx manual, but still simple enough to be reasonably kept in a single file.

You can obtain C++ and VHDL equivalents of the examples on this page by uploading the Arx code to the Arx Web Demo page. You can then simulate the outcome with the provided testbenches provided that you have first downloaded the infrastructure files available from the demo page. Feel free to experiment with your own variants of the IP blocks or completely new designs.

The C++ testbenches contain some knowledge of the application. The VHDL testbenches verify behavior on a clock-cycle basis using data generated with the C++ testbench. The .in files contain the inputs and the .ref files the expected output. The VHDL testbenches generate a .out file that should have the same content as the .ref file.

This page is under development. You can subscribe to the Bibix mailing list via the form on the Bibix home page to remain informed about new additions to this page and other developments related to Bibix.

Click on the file names in the table below to retrieve the code that you need (or use your right mouse button to save the files).

Description	Arx code	C++ testbench	VHDL testbench
Generic FIR filter similar to fir_gen from [1]	fir_gen.arx	tb_fir_gen.cpp	-
Pipelined CORDIC supporting rotation and vectoring modes	cordic_pipe.arx	tb_cordic_pipe.cpp	tb_cordic_pipe.vhd cordic_pipe.in cordic_pipe.ref
Application of pipelined CORDIC for sine/cosine generation	cordic_sine_gen.arx	tb_cordic_sine_gen.cpp	tb_cordic_sine_gen.vhd cordic_sine_gen.in cordic_sine_gen.ref
16-point decimation-in-frequency textbook FFT	fft_r2_16p.arx	tb_fft_r2_16p.cpp fft_r2_16p.dec	tb_fft_r2_16p.vhd fft_r2_16p.in fft_r2_16p.ref
Radix 2^3 decimation-in-frequency butterfly, see [2] and [3] for the theory.	fft_r8_bf.arx	tb_fft_r8_bf.cpp fft_r8_bf.dec	tb_fft_r8_bf.vhd fft_r8_bf.in fft_r8_bf.ref
64-point decimation-in-frequency FFT pipeline built from two radix 2^3 butterflies as given above.	fft_r8_64p.arx	tb_fft_r8_64p.cpp fft_r8_64p.dec	tb_fft_r8_64p.vhd fft_r8_64p.in fft_r8_64p.ref

References

[1]

Meyer-Baese, U., Digital Signal Processing with Field Programmable Gate Arrays, Third Edition, Springer, Berlin, (2007).

[2]

He, S. and M. Torkelson, "Designing Pipeline FFT Processor for OFDM (De)modulation", URSI International Symposium on Signals, Systems and Electronics, ISSSE'98, pp. 257-262, (1998).

[3]

Kampen, D. van, K.L. Hofstra, J. Potman and S.H. Gerez, "Implementation of a Combined OFDM-Demodulation and WCDMA-Equalization Module", Annual Workshop on Circuits, Systems and Signal Processing, ProRISC 2006, Veldhoven, The Netherlands, (November 2006). [download]