Digital Integrated Circuit Design


This course gives an in-depth treatment of various topics in the field of digital IC design. The focus is on presenting concepts and theory. First, a bottom-up approach is followed reviewing aspects of transistor and gate-level design relevant for digital circuits as well as the role of clocking. The understanding of these fundamental topics allows addressing the central hardware-design problem which is architecture design and the mapping of algorithms on that architecture. The course also pays ample attention to all kind of practical issues related to design, ranging from verification of behavior, timing analysis, power consumption, layout design and economic considerations.


The target audience for this course is professional who intends to become a digital IC designer. One can think of an analog IC designer, an electronic engineer with a specialization outside IC design or an non-electronic engineer who has followed the course Fundamentals of RTL Digital Design or possesses equivalent knowledge.

A second target audience is formed by managers of digital designers without personal background in digital IC design.


  • Transistor-level and gate-level design. Combinational logic with simple and complex gates, latches and flipflops, on-chip memories.

  • Synchronous design and clocking. Single-edge-triggered clocking and alternatives. Clock distribution, clock skew, clock trees, clock gating. Synchronization and metastability.

  • From algorithms to architectures. A review of implementation architectures: general-purpose processors, co-processors, application-specific processors, reconfigurable computing platforms. Resource sharing: scheduling and assignment. Transformations: pipelining, retiming, unfolding, etc.

  • Functional verification, simulation, building testbenches, transaction-level modeling, assertions, code coverage, quality metrics, etc.

  • Energy efficiency. Sources of energy dissipation in CMOS. Design for low power.

  • Physical aspects. Static timing analysis. Layout design, power and clock planning, floorplanning, placing and routing. Layout extraction, backannotation, layout versus schematic. Packaging.

  • Economic aspects. Recurring and non-recurring costs. IP, hard and soft modules. Fabrication for small quantities, multi-project wafers, etc. Future trends.

Course Organization and Material

The course will consist of about 24 hours of teaching sessions (lectures, as well as some paper-and-pencil problems, but no exercises requiring design tools). So, the course could e.g. be organized as a three-day course or a sequence of 8 weekly sessions of 3 hours each.

The study material will consist of lecture slides based on the following book (currently out of print, but available as e-book):

Kaeslin, H., Digital Integrated Circuit Design, From VLSI Architectures to CMOS Fabrication, Cambridge University Press, (2008).


Interested? Please contact Bibix to discuss how this course can be offered to you. Adaptation to your specific wishes may be possible.